<div dir="ltr"><div dir="auto">Mike,<div dir="auto"> I was native compiling on A72 (64 bit) using libgmp version 10.2.</div><div dir="auto"><br></div><div> Thanks,</div><div>-vijay</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Feb 7, 2017 7:21 PM, "Mike Mohr" <<a href="mailto:akihana@gmail.com" target="_blank">akihana@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="auto">Licensing issues are indeed thorny. Why can't openssl perform a dynamic link? The soversion should handle any ABI issues introduced in later versions of GMP.<div dir="auto"><br></div><div dir="auto">Are you cross compiling GMP for your use on a target device? If so, you'll need to ensure that the MPN_PATH is set appropriately. If you don't do so, you'll get the generic c code instead of optimized assembly routines. The performance difference can be dramatic, potentially several orders of magnitude. I had to deal with this myself when cross compiling GMP for Android.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Feb 7, 2017 4:51 PM, "Vijay Chander" <<a href="mailto:vijay.chander@gmail.com" target="_blank">vijay.chander@gmail.com</a>> wrote:<br type="attribution"><blockquote class="m_7885404389340633517m_-6140046958961099185quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="auto">Yes. Already took Andy's word from his previous replies for precisely this reason. <div dir="auto"><br></div><div dir="auto">GMP exercise was easy enough to get it out of the way. </div><div dir="auto"><br></div><div dir="auto">Thanks, </div><font color="#888888"><div dir="auto">Vijay </div></font></div><div class="m_7885404389340633517m_-6140046958961099185elided-text"><div class="gmail_extra"><br><div class="gmail_quote">On Feb 7, 2017 4:46 PM, "Jakob Bohm" <<a href="mailto:jb-openssl@wisemo.com" target="_blank">jb-openssl@wisemo.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">OpenSSL also has a lot of handwritten assembly language for ARM,<br>
x86 etc. Most of it written by Andy Polyakov.<br>
<br>
His response about what can and cannot be done on various ARM CPU<br>
models is most probably a result of this work.<br>
<br>
Also, OpenSSL has a more permissive license than the GMP, so using<br>
GMP in OpenSSL would cause problems for many OpenSSL using<br>
applications.<br>
<br>
On 08/02/2017 00:31, Mike Mohr wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Have you considered using GMP as a big integer backed for openssl? It<br>
has support for several arm variants using handwritten assembly code<br>
and the developers go to great lengths to find optimize runtime on all<br>
supported platforms.<br>
<br>
On Feb 7, 2017 2:26 PM, "Vijay Chander" <<a href="mailto:vijay.chander@gmail.com" target="_blank">vijay.chander@gmail.com</a><br>
<mailto:<a href="mailto:vijay.chander@gmail.com" target="_blank">vijay.chander@gmail.co<wbr>m</a>>> wrote:<br>
<br>
Andy,<br>
1:2.5 is pretty in my opinion for ARM !<br>
<br>
We will check out Mongoose.<br>
<br>
Hmm - will try to get to the bottom of those cache misses (at a<br>
lower priority).<br>
<br>
Thanks,<br>
-vijay<br>
<br>
<br>
On Tue, Feb 7, 2017 at 11:07 AM, Andy Polyakov <<a href="mailto:appro@openssl.org" target="_blank">appro@openssl.org</a><br>
<mailto:<a href="mailto:appro@openssl.org" target="_blank">appro@openssl.org</a>>> wrote:<br>
<br>
> A72 is running 1GHz compared to x86 at 2.1Ghz. So that should hopefully<br>
> get down to -1:5.<br>
<br>
And Mongoose will take you to ~1:2.5 (scaled to same frequency<br>
that is).<br>
Which I'd say is a fair result. Well, still could have been a bit<br>
better, but it's not unreasonable given ISA differences. Keep<br>
in mind<br>
that presented x86_64 result is for code utilizing<br>
Intel-specific code<br>
extensions.<br>
<br>
> There is no L3 cache on the A72 eval board and performance<br>
counters do<br>
> show 9x more DRAM accesses for ARM compared to x86.<br>
<br>
This is unexpected, because it takes *less* references to<br>
memory to<br>
perform it on ARMv8. Because it has larger register bank. And<br>
cache<br>
requirement is not that high for L3 to kick in... But at any<br>
case memory<br>
is not bottleneck here...<br>
<br>
</blockquote>
<br>
<br>
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<br>
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