Errored: openssl/openssl#38802 (master - 2621751)

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Mon Nov 30 12:59:24 UTC 2020

Build Update for openssl/openssl

Build: #38802
Status: Errored

Duration: 1 hr, 6 mins, and 13 secs
Commit: 2621751 (master)
Author: Ard Biesheuvel
Message: aes/asm/ avoid 32-bit lane assignment in CTR mode

ARM Cortex-A57 and Cortex-A72 cores running in 32-bit mode are affected
by silicon errata #1742098 [0] and #1655431 [1], respectively, where the
second instruction of a AES instruction pair may execute twice if an
interrupt is taken right after the first instruction consumes an input
register of which a single 32-bit lane has been updated the last time it
was modified.

This is not such a rare occurrence as it may seem: in counter mode, only
the least significant 32-bit word is incremented in the absence of a
carry, which makes our counter mode implementation susceptible to these

So let's shuffle the counter assignments around a bit so that the most
recent updates when the AES instruction pair executes are 128-bit wide.

[0] ARM-EPM-049219 v23 Cortex-A57 MPCore Software Developers Errata Notice
[1] ARM-EPM-012079 v11.0 Cortex-A72 MPCore Software Developers Errata Notice

Signed-off-by: Ard Biesheuvel <ard.biesheuvel at>

Reviewed-by: Paul Dale <paul.dale at>
Reviewed-by: Tomas Mraz <tmraz at>
(Merged from

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