[openssl/openssl] 03ce37: riscv: Provide a vector only implementation of Cha...

[Yangyu Chen]

  Branch: refs/heads/master
  Home:   https://github.com/openssl/openssl
  Commit: 03ce37e11729bbe9964bd613c0eed6156b920208
      https://github.com/openssl/openssl/commit/03ce37e11729bbe9964bd613c0eed6156b920208
  Author: Yangyu Chen <cyy at cyyself.name>
  Date:   2024-05-08 (Wed, 08 May 2024)

  Changed paths:
    A crypto/chacha/asm/chacha-riscv64-v-zbb.pl
    R crypto/chacha/asm/chacha-riscv64-zbb-zvkb.pl
    M crypto/chacha/build.info
    M crypto/chacha/chacha_riscv.c
    M crypto/perlasm/riscv.pm

  Log Message:
  -----------
  riscv: Provide a vector only implementation of Chacha20 cipher

Although we have a Zvkb version of Chacha20, the Zvkb from the RISC-V
Vector Cryptography Bit-manipulation extension was ratified in late 2023
and does not come to the RVA23 Profile. Many CPUs in 2024 currently do not
support Zvkb but may have Vector and Bit-manipulation, which are already in
the RVA22 Profile. This commit provides a vector-only implementation that
replaced the vror with vsll+vsrl+vor and can provide enough speed for
Chacha20 for new CPUs this year.

Signed-off-by: Yangyu Chen <cyy at cyyself.name>

Reviewed-by: Paul Dale <ppzgs1 at gmail.com>
Reviewed-by: Tomas Mraz <tomas at openssl.org>
(Merged from https://github.com/openssl/openssl/pull/24069)


  Commit: c857205407a0a074baf0db7fa7237a469f297c83
      https://github.com/openssl/openssl/commit/c857205407a0a074baf0db7fa7237a469f297c83
  Author: Yangyu Chen <cyy at cyyself.name>
  Date:   2024-05-08 (Wed, 08 May 2024)

  Changed paths:
    M crypto/chacha/asm/chacha-riscv64-v-zbb.pl

  Log Message:
  -----------
  chacha-riscv64-v-zbb.pl: add comment about vector register allocation

Since we can do group operations on vector registers in RISC-V, some vector
registers will be used without being explicitly referenced. Thus, comments
on vector register allocation should be added to improve the code
readability and maintainability.

Signed-off-by: Yangyu Chen <cyy at cyyself.name>

Reviewed-by: Paul Dale <ppzgs1 at gmail.com>
Reviewed-by: Tomas Mraz <tomas at openssl.org>
(Merged from https://github.com/openssl/openssl/pull/24069)


  Commit: f6ce48f5b8ad4d8d748ea87d2490cbed08db9936
      https://github.com/openssl/openssl/commit/f6ce48f5b8ad4d8d748ea87d2490cbed08db9936
  Author: Yangyu Chen <cyy at cyyself.name>
  Date:   2024-05-08 (Wed, 08 May 2024)

  Changed paths:
    M crypto/chacha/asm/chacha-riscv64-v-zbb.pl

  Log Message:
  -----------
  chacha-riscv64-v-zbb.pl: better format

This patch merged the `add` and `xor` part of chacha_sub_round, which are
same in RISC-V Vector only and Zvkb implementation. There is no change to
the generated ASM code except for the indent.

Signed-off-by: Yangyu Chen <cyy at cyyself.name>

Reviewed-by: Paul Dale <ppzgs1 at gmail.com>
Reviewed-by: Tomas Mraz <tomas at openssl.org>
(Merged from https://github.com/openssl/openssl/pull/24069)


Compare: https://github.com/openssl/openssl/compare/7cbca5a6d6e7...f6ce48f5b8ad

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