[openssl-dev] OpenSSL 1.1.0 pre 6: SPARCv9 capability bits problem
Rainer Jung
rainer.jung at kippdata.de
Thu Aug 4 16:57:02 UTC 2016
The following change introduced build problems:
Am 25.04.2016 um 11:51 schrieb Andy Polyakov:
> The branch master has been updated
> via 299ccadcdb99001c618d188fb243c1caaaa86a1c (commit)
> from a82a9f71ad0149380a680cae4c0cc693e6324679 (commit)
>
>
> - Log -----------------------------------------------------------------
> commit 299ccadcdb99001c618d188fb243c1caaaa86a1c
> Author: Andy Polyakov <appro at openssl.org>
> Date: Sat Apr 23 19:10:04 2016 +0200
>
> crypto/sparc_arch.h: reserve more SPARCv9 capability bits.
>
> Reviewed-by: Richard Levitte <levitte at openssl.org>
>
> -----------------------------------------------------------------------
>
> Summary of changes:
> crypto/sparc_arch.h | 9 ++++++++-
> crypto/sparcv9cap.c | 17 ++++++++++++-----
> 2 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/crypto/sparc_arch.h b/crypto/sparc_arch.h
> index 6f8969f..5bcdd9f 100644
> --- a/crypto/sparc_arch.h
> +++ b/crypto/sparc_arch.h
> @@ -5,12 +5,16 @@
> # define SPARCV9_PREFER_FPU (1<<1)
> # define SPARCV9_VIS1 (1<<2)
> # define SPARCV9_VIS2 (1<<3)/* reserved */
> -# define SPARCV9_FMADD (1<<4)/* reserved for SPARC64 V */
> +# define SPARCV9_FMADD (1<<4)
> # define SPARCV9_BLK (1<<5)/* VIS1 block copy */
> # define SPARCV9_VIS3 (1<<6)
> # define SPARCV9_RANDOM (1<<7)
> # define SPARCV9_64BIT_STACK (1<<8)
> # define SPARCV9_FJAESX (1<<9)/* Fujitsu SPARC64 X AES */
> +# define SPARCV9_FJDESX (1<<10)/* Fujitsu SPARC64 X DES, reserved */
> +# define SPARCV9_FJHPCACE (1<<11)/* Fujitsu HPC-ACE, reserved */
> +# define SPARCV9_IMA (1<<13)/* reserved */
> +# define SPARCV9_VIS4 (1<<14)/* reserved */
>
> /*
> * OPENSSL_sparcv9cap_P[1] is copy of Compatibility Feature Register,
> @@ -29,6 +33,9 @@
> # define CFR_MONTMUL 0x00000200/* Supports MONTMUL opcodes */
> # define CFR_MONTSQR 0x00000400/* Supports MONTSQR opcodes */
> # define CFR_CRC32C 0x00000800/* Supports CRC32C opcodes */
> +# define CFR_XMPMUL 0x00001000/* Supports XMPMUL opcodes */
> +# define CFR_XMONTMUL 0x00002000/* Supports XMONTMUL opcodes */
> +# define CFR_XMONTSQR 0x00004000/* Supports XMONTSQR opcodes */
>
> # if defined(OPENSSL_PIC) && !defined(__PIC__)
> # define __PIC__
> diff --git a/crypto/sparcv9cap.c b/crypto/sparcv9cap.c
> index e1e6d73..30c384b 100644
> --- a/crypto/sparcv9cap.c
> +++ b/crypto/sparcv9cap.c
> @@ -149,17 +149,24 @@ void OPENSSL_cpuid_setup(void)
> unsigned int vec[1];
The vec array still has size 1, but ...
> if (getisax (vec,1)) {
> - if (vec[0]&0x0020) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS1;
> - if (vec[0]&0x0040) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS2;
> - if (vec[0]&0x0080) OPENSSL_sparcv9cap_P[0] |= SPARCV9_BLK;
> - if (vec[0]&0x0100) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FMADD;
> - if (vec[0]&0x0400) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS3;
> + if (vec[0]&0x00020) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS1;
> + if (vec[0]&0x00040) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS2;
> + if (vec[0]&0x00080) OPENSSL_sparcv9cap_P[0] |= SPARCV9_BLK;
> + if (vec[0]&0x00100) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FMADD;
> + if (vec[0]&0x00400) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS3;
> + if (vec[0]&0x01000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FJHPCACE;
> + if (vec[0]&0x02000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FJDESX;
> + if (vec[0]&0x08000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_IMA;
> if (vec[0]&0x10000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FJAESX;
> + if (vec[1]&0x00008) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS4;
... here we use vec[1], so the compiler warns:
crypto/sparcv9cap.c:179:20: warning: array subscript is above array
bounds [-Warray-bounds]
if (vec[1]&0x00008) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS4;
^
I also can't check whether 0x00008 is correct for vec[1] (and we need
size 2) or 0x00008 should be something else. My Sparc system is too old
for VIS4.
> /* reconstruct %cfr copy */
> OPENSSL_sparcv9cap_P[1] = (vec[0]>>17)&0x3ff;
> OPENSSL_sparcv9cap_P[1] |= (OPENSSL_sparcv9cap_P[1]&CFR_MONTMUL)<<1;
> if (vec[0]&0x20000000) OPENSSL_sparcv9cap_P[1] |= CFR_CRC32C;
> + if (vec[1]&0x00000020) OPENSSL_sparcv9cap_P[1] |= CFR_XMPMUL;
> + if (vec[1]&0x00000040)
> + OPENSSL_sparcv9cap_P[1] |= CFR_XMONTMUL|CFR_XMONTSQR;
Again vec[1] (twice).
> /* Some heuristics */
> /* all known VIS2-capable CPUs have unprivileged tick counter */
Furthermore the following changes:
The branch master has been updated
via 6944565bd55d147bdb46c708dff06ac310457036 (commit)
via 4400f6c61e586dde2aea8dd023c9d4573fbbc547 (commit)
via fb65020b37d606659f90aa62163220b72d5560f5 (commit)
from 38c5674dda8333288aa5d57ccd046203803aa81f (commit)
- Log -----------------------------------------------------------------
commit 6944565bd55d147bdb46c708dff06ac310457036
Author: Andy Polyakov <appro at openssl.org>
Date: Tue Apr 19 13:09:54 2016 +0200
evp/aes_aes.c: engage Fujitsu SPARC64 X AES support.
Reviewed-by: Richard Levitte <levitte at openssl.org>
commit 4400f6c61e586dde2aea8dd023c9d4573fbbc547
Author: Andy Polyakov <appro at openssl.org>
Date: Tue Apr 19 13:08:47 2016 +0200
sparcv9cap.c: add Fujitsu SPARC64 X AES capability detection.
Reviewed-by: Richard Levitte <levitte at openssl.org>
commit fb65020b37d606659f90aa62163220b72d5560f5
Author: Andy Polyakov <appro at openssl.org>
Date: Tue Apr 19 13:06:18 2016 +0200
Add AES assembly module for Fujitsu SPARC64 X/X+.
Reviewed-by: Richard Levitte <levitte at openssl.org>
need the following patch to crypto/sparcv9cap.c here (warning "implicit
declaration of function '_sparcv9_fjaesx_probe'"):
@@ -93,6 +93,7 @@
void _sparcv9_fmadd_probe(void);
unsigned long _sparcv9_rdcfr(void);
void _sparcv9_vis3_probe(void);
+void _sparcv9_fjaesx_probe(void);
unsigned long _sparcv9_random(void);
size_t _sparcv9_vis1_instrument_bus(unsigned int *, size_t);
size_t _sparcv9_vis1_instrument_bus2(unsigned int *, size_t, size_t);
Thanks and regards,
Rainer
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