Compiling for RISC-V

Kristin Barber barber.m.kristin at gmail.com
Mon Mar 9 19:23:09 UTC 2020


I did also try configuring for "no-asm", but there still seemed to be
architecture-specific issues based on which files the errors were coming
from.  I should probably also mention that I am attempting to cross-compile
for RV64 from an x86 machine.

On Mon, Mar 9, 2020 at 3:12 PM Scott Neugroschl <scott_n at xypro.com> wrote:

>
>
> Is the “no-asm” configuration option still supported?
>
>
>
> *From:* openssl-users <openssl-users-bounces at openssl.org> *On Behalf Of *Kristin
> Barber
> *Sent:* Monday, March 9, 2020 12:03 PM
> *To:* Richard Levitte <levitte at openssl.org>
> *Cc:* openssl-users at openssl.org
> *Subject:* Re: Compiling for RISC-V
>
>
>
> Hi Richard, thanks for the reply. It was helpful.
>
>
>
> You are correct, I was able to find a configuration that worked by passing
> the RISC-V compiler via "make variable" assignment, along with some
> relevant options.  Things start compiling, but the build fails on what
> seems to be architecture-specific assembly files which are selected based
> on which "platform" has been configured.  It did not seem to me that there
> were RISC-V assembly-specific files as an option here, and based on your
> reply, I think that is indeed the issue.  Am I understanding this correctly?
>
>
>
> Thanks,
>
>
>
> Kristin
>
>
>
> On Mon, Mar 9, 2020 at 3:03 AM Richard Levitte <levitte at openssl.org>
> wrote:
>
> On Mon, 09 Mar 2020 05:18:17 +0100,
> Kristin Barber wrote:
> > I've looked at the INSTALL docs, and it doesn't seem that RISC-V
> processors are supported
> > currently as a platform. Is this correct?
>
> That is correct.  No one has implemented that support yet.
>
> > Is there a branch which enables configuring for a RISC-V machine that
> hasn't yet made it into a
> > stable release?
>
> Not that I know of.  Although, this same question has also been raised
> on github (I forget the issue number).
>
> > Any advice on where to look for information or changes to the build
> process in order to compile
> > for RISC-V?
>
> The first thing to attempt is a generic build with no assembler.
> There are some really simply config targets that could be a first
> step, one of:
>
>     ./Configure cc
>
>     ./Configure gcc
>
> A (pretty big) step up from that, at least if Linux is your target,
> would be one of these:
>
>     ./Configure linux-generic32
>
>     ./Configure linux-generic64
>
> Note that in either case, you may have to add C flags and ld flags,
> which you can do in one of two ways:
>
> 1)  directly on the configuration command line, like this (Configure
>     makes an educated guess on what flags go where):
>
>     ./Configure linux-generic64 -m64 -DWHATEVER=value -Wl,-something
>
> 2)  via "make variable" assignment:
>
>     ./Configure linux-generic64 \
>                 CPPFLAGS='-DWHATEVER=value' \
>                 CFLAGS='-m64' \
>                 LDFLAGS='-Wl,-something'
>
> At some point, you might find a combination that works for you.  We
> would definitely like to know what you figure out, and it may be that
> the result makes it into our database of config targets (which, if
> you're curious, are the files Configurations/*.conf).
>
> Now, configuration is the easy bit when it comes to new CPUs,
> relatively speaking.  I assume that part of your question is whether
> there is assembler support.  This is the hard part in terms of
> effort.  We currently have no such thing at all for RISC-V, and I
> haven't seen any attempts to start such an effort...  PRs would
> certainly be welcome, but anyone who tries this will have to be
> prepared for it to take a while to get into the main source.
>
> Cheers,
> Richard
>
> --
> Richard Levitte         levitte at openssl.org
> OpenSSL Project         http://www.openssl.org/~levitte/
> <https://linkprotect.cudasvc.com/url?a=http%3a%2f%2fwww.openssl.org%2f~levitte%2f&c=E,1,X0wuSd-kz2nVhT_NOTOEEEyCfRQ3PVlEpzPg7qMVOE18vBdtM4EJjJ0PDdArARBsvQZdWJpbcy94bbUgzuKmj9jsBIiAzT87yPNJQ_aU-tOjP9VR4huaxBYl6g,,&typo=1>
>
>
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