[openssl-dev] [openssl.org #4645] Multi Block (MB) SHA384 for x86_64 architectures that support AVX2/AVX512 instructions set

[Gueron, Shay via RT]

Hello all,

This patch is a contribution to OpenSSL.

It includes a Multi Block (MB) SHA384 implementation.

The patch adds Multi Block feature for SHA384 Hashing as a standalone.
The patch includes SHA384 Multi Block implementation for x86_64 architecture that support AVX2 & AVX512.

This patch enhances the performance of parallelized hashing on SHA384, and adds the feature of standalone Multi Block using the OpenSSL API.

The performance gains can be observed by invoking "openssl speed -mb -evp sha384", which was also added to "speed".

This patch extends over the previous patches [1,[2],[3], and incorporates them as well.

The patch requires updated binutils (tested with binutils version 2.25) and gcc (tested with gcc 5.2.0).

Results: using "speed" on 8192 bytes buffers input(in cycles/byte)

            SHA384 One Buffer           SHA384 - Multi Block
    HSW:    5.90                        3.85
    BDW:    5.43                        3.62
    SKL:    5.29                        3.38

Speedup of SHA384 Multi Block compared to one buffer (8192 bytes input):
            SHA384 - Multi Block
    HSW:   1.53x
    BDW:   1.5x
    SKL:   1.56x



[1] Patch #3850 - Improved performance Multi Block CBC-SHA1 and CBC-SHA256.
https://mta.openssl.org/pipermail/openssl-dev/2015-May/001417.html

[2] Patch #4221 - Accelerating Multi Block (MB) CBC SHA256 on architectures that support AVX512 instructions set
http://openssl.6102.n7.nabble.com/openssl-org-4221-PATCH-Accelerating-Multi-Block-MB-CBC-SHA256-on-architectures-that-support-AVX512-it-td62058.html

[3] Patch #4307 - Multi Block (MB) SHA512 for x86_64 architectures that support AVX2/AVX512 instructions set
http://openssl.6102.n7.nabble.com/openssl-org-4307-PATCH-Multi-Block-MB-SHA512-for-x86-64-Architectures-that-support-AVX2-AVX512-instrt-td63716.html

Developers and authors:
***************************************************************************
Shay Gueron (1, 2), Regev Shemy (2)
(1) University of Haifa, Israel
(2) Intel Corporation, Israel Development Center, Haifa, Israel
***************************************************************************




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